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| author | Elaine Zhang <[email protected]> | 2018-06-15 02:16:50 +0000 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2018-07-06 17:17:57 +0000 |
| commit | 956060a52795a060833e8de2d1bb89209e61bed2 (patch) | |
| tree | 2cc5d99d9e264bad467efcc7f3458d9875b4743f /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | Merge branch 'v4.19-shared/clkids' into v4.19-clk/next (diff) | |
| download | kernel-956060a52795a060833e8de2d1bb89209e61bed2.tar.gz kernel-956060a52795a060833e8de2d1bb89209e61bed2.zip | |
clk: rockchip: add support for half divider
The new Rockchip socs have optional half divider:
The formula is shown as:
freq_out = 2*freq_in / (2*div + 3)
Is this the same for all of new SoCs.
So we use "branch_half_divider" + "COMPOSITE_NOMUX_HALFDIV \
DIV_HALF \ COMPOSITE_HALFDIV \ CMPOSITE_NOGATE_HALFDIV"
to hook that special divider clock-type into our clock-tree.
Signed-off-by: Elaine Zhang <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions