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| author | Sohil Mehta <[email protected]> | 2017-12-20 19:59:24 +0000 |
|---|---|---|
| committer | Joerg Roedel <[email protected]> | 2018-01-17 14:02:49 +0000 |
| commit | 5e3b4a15dd8da6bded2092694c8db3b505cbf711 (patch) | |
| tree | 34c9140038e015b08883a693734e95ced01512c9 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | iommu/vt-d: Use domain instead of cache fetching (diff) | |
| download | kernel-5e3b4a15dd8da6bded2092694c8db3b505cbf711.tar.gz kernel-5e3b4a15dd8da6bded2092694c8db3b505cbf711.zip | |
iommu/vt-d: Enable upto 57 bits of domain address width
Update the IOMMU default domain address width to 57 bits. This would
enable the IOMMU to do upto 5-levels of paging for second level
translations - IOVA translation requests without PASID.
Even though the maximum supported address width is being increased to
57, __iommu_calculate_agaw() would set the actual supported address
width to the maximum support available in IOMMU hardware.
Signed-off-by: Sohil Mehta <[email protected]>
Signed-off-by: Joerg Roedel <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions