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authorShubhrajyoti Datta <[email protected]>2023-06-20 11:01:37 +0000
committerStephen Boyd <[email protected]>2023-07-19 20:09:54 +0000
commit64446fe08c55dfa1f4489bc6366545c7180268b8 (patch)
tree482f39cae56aedf887c88a86522fdbe297e3ea8b /tools/perf/scripts/python/stat-cpi.py
parentdt-bindings: clock: ast2600: Add I3C and MAC reset definitions (diff)
downloadkernel-64446fe08c55dfa1f4489bc6366545c7180268b8.tar.gz
kernel-64446fe08c55dfa1f4489bc6366545c7180268b8.zip
dt-bindings: clock: versal: Add versal-net compatible string
Add dt-binding documentation for Versal NET platforms. Versal Net is a new AMD/Xilinx SoC. The SoC and its architecture is based on the Versal ACAP device. The Versal Net device includes more security features in the platform management controller (PMC) and increases the number of CPUs in the application processing unit (APU) and the real-time processing unit (RPU). Signed-off-by: Jay Buddhabhatti <[email protected]> Signed-off-by: Shubhrajyoti Datta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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