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| author | Charles Keepax <[email protected]> | 2019-06-27 08:55:17 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2019-06-27 21:17:30 +0000 |
| commit | f9d3fb22ab27aaee8748480fe3fa8cc17875ee30 (patch) | |
| tree | c143b6ba03285e65317010188441a4e113cc26d8 /tools/perf/scripts/python/stackcollapse.py | |
| parent | clk: lochnagar: Use new parent_data approach to register clock parents (diff) | |
| download | kernel-f9d3fb22ab27aaee8748480fe3fa8cc17875ee30.tar.gz kernel-f9d3fb22ab27aaee8748480fe3fa8cc17875ee30.zip | |
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
This clock was missed when the binding was initially merged but is
supported by the driver, so add it to the binding document.
Signed-off-by: Charles Keepax <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions