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| author | Atish Patra <[email protected]> | 2020-04-03 01:46:09 +0000 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2020-04-17 07:59:28 +0000 |
| commit | d727be7bbf7b68ccc18a3278469325d8f486d75b (patch) | |
| tree | 351489f538a56d684e7f462da3026aee5a4c8710 /tools/perf/scripts/python/stackcollapse.py | |
| parent | irqchip/ti-sci-inta: Fix processing of masked irqs (diff) | |
| download | kernel-d727be7bbf7b68ccc18a3278469325d8f486d75b.tar.gz kernel-d727be7bbf7b68ccc18a3278469325d8f486d75b.zip | |
irqchip/sifive-plic: Fix maximum priority threshold value
As per the PLIC specification, maximum priority threshold value is 0x7
not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed,
there may be some implementation which checks the upper bound resulting in
an illegal access.
Fixes: ccbe80bad571 ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline")
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions