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| author | Shubhrajyoti Datta <[email protected]> | 2023-12-15 05:33:52 +0000 |
|---|---|---|
| committer | Borislav Petkov (AMD) <[email protected]> | 2023-12-15 12:01:27 +0000 |
| commit | 9483aa44912f26da2b69dade6099c2bf4b50a8c3 (patch) | |
| tree | 5471005218f692b81ca1a73fd74f8ea45f9fb144 /tools/perf/scripts/python/stackcollapse.py | |
| parent | Linux 6.7-rc5 (diff) | |
| download | kernel-9483aa44912f26da2b69dade6099c2bf4b50a8c3.tar.gz kernel-9483aa44912f26da2b69dade6099c2bf4b50a8c3.zip | |
EDAC/versal: Read num_csrows and num_chans using the correct bitfield macro
Fix the extraction of num_csrows and num_chans. The extraction of the
num_rows is wrong. Instead of extracting using the FIELD_GET it is
calling FIELD_PREP.
The issue was masked as the default design has the rows as 0.
Fixes: 6f15b178cd63 ("EDAC/versal: Add a Xilinx Versal memory controller driver")
Closes: https://lore.kernel.org/all/[email protected]/
Reported-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Shubhrajyoti Datta <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions