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| author | Siddharth Vadapalli <[email protected]> | 2023-03-15 09:24:08 +0000 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2023-04-12 16:38:00 +0000 |
| commit | 73b46467cac027fe6cbe6585946726b53b80bfdb (patch) | |
| tree | 78ee5f825a38134831f6b1fb3a118765059d4441 /tools/perf/scripts/python/stackcollapse.py | |
| parent | phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select() (diff) | |
| download | kernel-73b46467cac027fe6cbe6585946726b53b80bfdb.tar.gz kernel-73b46467cac027fe6cbe6585946726b53b80bfdb.zip | |
dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G
The CPSW9G instance of CPSW Ethernet Switch on TI's J784S4 SoC supports
additional PHY modes like QSGMII. Add a compatible for it.
Enable the use of "ti,qsgmii-main-ports" property for J784S4 CPSW9G.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions