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| author | Thierry Reding <[email protected]> | 2014-04-04 13:55:13 +0000 |
|---|---|---|
| committer | Peter De Schrijver <[email protected]> | 2014-04-17 11:12:34 +0000 |
| commit | d0f02ce3b1685ef6ffe43692034599790f83e7ab (patch) | |
| tree | 08b7289a4e5db66417e3d1455577345f29114ed1 /tools/perf/scripts/python/sctop.py | |
| parent | Linux 3.15-rc1 (diff) | |
| download | kernel-d0f02ce3b1685ef6ffe43692034599790f83e7ab.tar.gz kernel-d0f02ce3b1685ef6ffe43692034599790f83e7ab.zip | |
clk: tegra: Fix PLLE programming
PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider fields
the corresponding masks were never shifted, thereby clearing only the
lowest bits of the register. This lead to a situation where the PLLE
programming would only work if the register hadn't been touched before.
Signed-off-by: Thierry Reding <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/sctop.py')
0 files changed, 0 insertions, 0 deletions