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| author | Srinivas Pandruvada <[email protected]> | 2019-09-05 23:37:47 +0000 |
|---|---|---|
| committer | Andy Shevchenko <[email protected]> | 2019-09-09 10:19:35 +0000 |
| commit | 92e0e87d0be5eb192fab1edb9b44e724c63416ce (patch) | |
| tree | d35c7831e8dc939d40fe8fcd4a45999d9b5dcf62 /tools/perf/scripts/python/sctop.py | |
| parent | tools/power/x86/intel-speed-select: Fix memory leak (diff) | |
| download | kernel-92e0e87d0be5eb192fab1edb9b44e724c63416ce.tar.gz kernel-92e0e87d0be5eb192fab1edb9b44e724c63416ce.zip | |
platform/x86: ISST: Allow additional TRL MSRs
Additional Turbo Ratio Limit (TRL) MSRs are required to get bucket vs core
count relationship. So add them to the list of allowed MSRs.
Signed-off-by: Srinivas Pandruvada <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/sctop.py')
0 files changed, 0 insertions, 0 deletions