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| author | Harry Pan <[email protected]> | 2017-07-17 10:37:49 +0000 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2017-07-18 12:13:40 +0000 |
| commit | 5c10b048c37cc08a21fa97a0575eccf4948948ca (patch) | |
| tree | 8ac4591d4beb63293a88d4d69fd7d6505629edeb /tools/perf/scripts/python/sctop.py | |
| parent | Merge tag 'perf-urgent-for-mingo-4.13-20170712' of git://git.kernel.org/pub/s... (diff) | |
| download | kernel-5c10b048c37cc08a21fa97a0575eccf4948948ca.tar.gz kernel-5c10b048c37cc08a21fa97a0575eccf4948948ca.zip | |
perf/x86/intel: Enable C-state residency events for Apollo Lake
Goldmont microarchitecture supports C1/C3/C6, PC2/PC3/PC6/PC10 state
residency counters, the patch enables them for Apollo Lake platform.
The MSR information is based on Intel Software Developers' Manual,
Vol. 4, Order No. 335592, Table 2-6 and 2-12.
Signed-off-by: Harry Pan <[email protected]>
Cc: Alexander Shishkin <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Jiri Olsa <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Stephane Eranian <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Vince Weaver <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
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