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authorJoseph Lo <[email protected]>2019-02-21 07:21:43 +0000
committerDaniel Lezcano <[email protected]>2019-02-23 11:13:45 +0000
commit87e0a455960a383a60d9af49ba74fb1c87b20016 (patch)
treeb489468a93dedac4e0426801ee2afa65222ba746 /tools/perf/scripts/python/sched-migration.py
parentclocksource/drivers/timer-cs5535: Rename the file for consistency (diff)
downloadkernel-87e0a455960a383a60d9af49ba74fb1c87b20016.tar.gz
kernel-87e0a455960a383a60d9af49ba74fb1c87b20016.zip
dt-bindings: timer: add Tegra210 timer
The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic, or watchdog interrupts. Cc: Daniel Lezcano <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Joseph Lo <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Jon Hunter <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]>
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