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| author | Peng Fan <[email protected]> | 2023-06-25 12:33:40 +0000 |
|---|---|---|
| committer | Abel Vesa <[email protected]> | 2023-08-14 09:29:52 +0000 |
| commit | 7653a59be8af043adc4c09473975a860e6055ff9 (patch) | |
| tree | acd12f7024ed6ae5d7bef1caea9c8b7dab7c9a96 /tools/perf/scripts/python/sched-migration.py | |
| parent | clk: imx: pllv4: Fix SPLL2 MULT range (diff) | |
| download | kernel-7653a59be8af043adc4c09473975a860e6055ff9.tar.gz kernel-7653a59be8af043adc4c09473975a860e6055ff9.zip | |
clk: imx: imx8ulp: update SPLL2 type
The SPLL2 on iMX8ULP is different with other frac PLLs, it can
support VCO from 650Mhz to 1Ghz. Following the changes to pllv4,
use the new type IMX_PLLV4_IMX8ULP_1GHZ.
Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp")
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/sched-migration.py')
0 files changed, 0 insertions, 0 deletions