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| author | Nishanth Menon <[email protected]> | 2014-05-16 10:46:00 +0000 |
|---|---|---|
| committer | Tero Kristo <[email protected]> | 2014-06-06 17:33:40 +0000 |
| commit | 7e148070001ae82df08966199580a29b934e3bf3 (patch) | |
| tree | b15538c8e4192a723fef5ba6b81d4bde6fbd26a2 /tools/perf/scripts/python/net_dropmonitor.py | |
| parent | CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher f... (diff) | |
| download | kernel-7e148070001ae82df08966199580a29b934e3bf3.tar.gz kernel-7e148070001ae82df08966199580a29b934e3bf3.zip | |
ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with higher frequencies
OMAP5432, DRA75x and DRA72x have MPU DPLLs that need Duty Cycle
Correction(DCC) to operate safely at frequencies >= 1.4GHz.
Switch to "ti,omap5-mpu-dpll-clock" compatible property which provides
this support.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/net_dropmonitor.py')
0 files changed, 0 insertions, 0 deletions