diff options
| author | Gary R Hook <[email protected]> | 2017-12-20 16:47:08 +0000 |
|---|---|---|
| committer | Alex Williamson <[email protected]> | 2017-12-20 16:47:08 +0000 |
| commit | ff18c4e598de13af6503d6adb66f3ad768b6a53e (patch) | |
| tree | 43b81ef7179015b5793c6ffefd936af281ac7b11 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | iommu/amd - Record more information about unknown events (diff) | |
| download | kernel-ff18c4e598de13af6503d6adb66f3ad768b6a53e.tar.gz kernel-ff18c4e598de13af6503d6adb66f3ad768b6a53e.zip | |
iommu/amd: Set the device table entry PPR bit for IOMMU V2 devices
The AMD IOMMU specification Rev 3.00 (December 2016) introduces a
new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register
offset 0030h (IOMMU Extended Feature Register).
When EPHSup=1, the IOMMU hardware requires the PPR bit of the
device table entry (DTE) to be set in order to support PPR for a
particular endpoint device.
Please see https://support.amd.com/TechDocs/48882_IOMMU.pdf for
this revision of the AMD IOMMU specification.
Signed-off-by: Gary R Hook <[email protected]>
Signed-off-by: Alex Williamson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions