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| author | Geert Uytterhoeven <[email protected]> | 2020-05-08 09:59:18 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2020-05-11 08:31:24 +0000 |
| commit | e47cb97f153193d4b41ca8d48127da14513d54c7 (patch) | |
| tree | b800cc520340c15f90dab6801613bc9812c1f0c1 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | ARM: dts: r7s9210: Remove bogus clock-names from OSTM nodes (diff) | |
| download | kernel-e47cb97f153193d4b41ca8d48127da14513d54c7.tar.gz kernel-e47cb97f153193d4b41ca8d48127da14513d54c7.zip | |
ARM: dts: r8a7740: Add missing extal2 to CPG node
The Clock Pulse Generator (CPG) device node lacks the extal2 clock.
This may lead to a failure registering the "r" clock, or to a wrong
parent for the "usb24s" clock, depending on MD_CK2 pin configuration and
boot loader CPG_USBCKCR register configuration.
This went unnoticed, as this does not affect the single upstream board
configuration, which relies on the first clock input only.
Fixes: d9ffd583bf345e2e ("ARM: shmobile: r8a7740: add SoC clocks to DTS")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Ulrich Hecht <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions
