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| author | Huacai Chen <[email protected]> | 2017-11-21 13:23:39 +0000 |
|---|---|---|
| committer | Martin K. Petersen <[email protected]> | 2017-11-22 04:06:32 +0000 |
| commit | c2e8fbf908afd81ad502b567a6639598f92c9b9d (patch) | |
| tree | da52dc8f0f0298711ddb13259e95e88668bf8a1d /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | scsi: use dma_get_cache_alignment() as minimum DMA alignment (diff) | |
| download | kernel-c2e8fbf908afd81ad502b567a6639598f92c9b9d.tar.gz kernel-c2e8fbf908afd81ad502b567a6639598f92c9b9d.zip | |
scsi: libsas: align sata_device's rps_resp on a cacheline
The rps_resp buffer in ata_device is a DMA target, but it isn't
explicitly cacheline aligned. Due to this, adjacent fields can be
overwritten with stale data from memory on non-coherent architectures.
As a result, the kernel is sometimes unable to communicate with an SATA
device behind a SAS expander.
Fix this by ensuring that the rps_resp buffer is cacheline aligned.
This issue is similar to that fixed by Commit 84bda12af31f93 ("libata:
align ap->sector_buf") and Commit 4ee34ea3a12396f35b26 ("libata: Align
ata_device's id on a cacheline").
Cc: [email protected]
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Christoph Hellwig <[email protected]>
Signed-off-by: Martin K. Petersen <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions