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| author | Rohit Visavalia <[email protected]> | 2025-02-10 11:36:14 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2025-06-21 21:48:06 +0000 |
| commit | af9019b5f1500222e878d5b7b5c924795b5f41fb (patch) | |
| tree | b1073a29dfb461c2a2000c4fbb4f2e153140354d /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | clk: xilinx: vcu: unregister pll_post only if registered correctly (diff) | |
| download | kernel-af9019b5f1500222e878d5b7b5c924795b5f41fb.tar.gz kernel-af9019b5f1500222e878d5b7b5c924795b5f41fb.zip | |
clk: xilinx: vcu: Update vcu init/reset sequence
Updated vcu init/reset sequence as per design changes.
If VCU reset GPIO is available then do assert and de-assert it before
enabling/disabling gasket isolation.
This GPIO is added because gasket isolation will be removed during startup
that requires access to SLCR register space. Post startup, the ownership of
the register interface lies with logiCORE IP.
Signed-off-by: Rohit Visavalia <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions