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| author | Garmin.Chang <[email protected]> | 2023-03-31 12:36:18 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2023-03-31 18:51:22 +0000 |
| commit | 4898e77f47e5b028a72c711c97841d74608e61ed (patch) | |
| tree | de6d00af1ccc4c43dcd32ff65f8888d8f78f2525 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | clk: mediatek: Add MT8188 vppsys0 clock support (diff) | |
| download | kernel-4898e77f47e5b028a72c711c97841d74608e61ed.tar.gz kernel-4898e77f47e5b028a72c711c97841d74608e61ed.zip | |
clk: mediatek: Add MT8188 vppsys1 clock support
Add MT8188 vppsys1 clock controller which provides clock gate
controller for Video Processor Pipe.
Signed-off-by: Garmin.Chang <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions