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| author | Huacai Chen <[email protected]> | 2018-09-05 09:33:09 +0000 |
|---|---|---|
| committer | Paul Burton <[email protected]> | 2018-10-16 06:11:14 +0000 |
| commit | 360fe725f8849aaddc53475fef5d4a0c439b05ae (patch) | |
| tree | 7402e2f230edc00746bf98dfdfb1cad6dd248b4a /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | MIPS: Loongson-3: Fix CPU UART irq delivery problem (diff) | |
| download | kernel-360fe725f8849aaddc53475fef5d4a0c439b05ae.tar.gz kernel-360fe725f8849aaddc53475fef5d4a0c439b05ae.zip | |
MIPS: Loongson-3: Fix BRIDGE irq delivery problem
After commit e509bd7da149dc349160 ("genirq: Allow migration of chained
interrupts by installing default action") Loongson-3 fails at here:
setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
This is because both chained_action and cascade_irqaction don't have
IRQF_SHARED flag. This will cause Loongson-3 resume fails because HPET
timer interrupt can't be delivered during S3. So we set the irqchip of
the chained irq to loongson_irq_chip which doesn't disable the chained
irq in CP0.Status.
Cc: [email protected]
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/20434/
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Cc: Huacai Chen <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions
