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| author | Jagan Teki <[email protected]> | 2023-07-31 11:00:00 +0000 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2023-08-10 21:14:06 +0000 |
| commit | 5c7a71fd82350c2f5828a66a1f2f38306d61cbc7 (patch) | |
| tree | 9c2c30d878163740e9bbe2ee55a454bb16ba2920 /tools/perf/scripts/python/libxed.py | |
| parent | clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz (diff) | |
| download | kernel-5c7a71fd82350c2f5828a66a1f2f38306d61cbc7.tar.gz kernel-5c7a71fd82350c2f5828a66a1f2f38306d61cbc7.zip | |
clk: rockchip: rv1126: Add PD_VO clock tree
PD_VO clock tree diagram in RV1126 is connected to
- BIU_VO
- VOP
- RGA
- IEP
- DSIHOST
Add entire PD_VO clock tree for rv1126.
Signed-off-by: Jagan Teki <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/libxed.py')
0 files changed, 0 insertions, 0 deletions