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authorCatalin Marinas <[email protected]>2021-05-14 09:50:01 +0000
committerCatalin Marinas <[email protected]>2021-05-14 16:11:16 +0000
commit588a513d34257fdde95a9f0df0202e31998e85c6 (patch)
tree053e87f91afc329f6a187eae1a2e29ecaf6a3eed /tools/perf/scripts/python/intel-pt-events.py
parentarm64: tools: Add __ASM_CPUCAPS_H to the endif in cpucaps.h (diff)
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arm64: Fix race condition on PG_dcache_clean in __sync_icache_dcache()
To ensure that instructions are observable in a new mapping, the arm64 set_pte_at() implementation cleans the D-cache and invalidates the I-cache to the PoU. As an optimisation, this is only done on executable mappings and the PG_dcache_clean page flag is set to avoid future cache maintenance on the same page. When two different processes map the same page (e.g. private executable file or shared mapping) there's a potential race on checking and setting PG_dcache_clean via set_pte_at() -> __sync_icache_dcache(). While on the fault paths the page is locked (PG_locked), mprotect() does not take the page lock. The result is that one process may see the PG_dcache_clean flag set but the I/D cache maintenance not yet performed. Avoid test_and_set_bit(PG_dcache_clean) in favour of separate test_bit() and set_bit(). In the rare event of a race, the cache maintenance is done twice. Signed-off-by: Catalin Marinas <[email protected]> Cc: <[email protected]> Cc: Will Deacon <[email protected]> Cc: Steven Price <[email protected]> Reviewed-by: Steven Price <[email protected]> Acked-by: Will Deacon <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Catalin Marinas <[email protected]>
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