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| author | Thierry Reding <[email protected]> | 2018-06-11 08:20:37 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2018-07-09 00:06:48 +0000 |
| commit | 8097d4c75f00f3fce8f4916521ec61ec0c607324 (patch) | |
| tree | 065722775d1cda36dfeb3e0d7c4acbc40e8aedd5 /tools/perf/scripts/python/futex-contention.py | |
| parent | clk: tegra: Make vic03 a child of pll_c3 (diff) | |
| download | kernel-8097d4c75f00f3fce8f4916521ec61ec0c607324.tar.gz kernel-8097d4c75f00f3fce8f4916521ec61ec0c607324.zip | |
clk: tegra: Make vde a child of pll_c3
The current default is to leave the VDE clock's parent at the default,
which is clk_m. However, that is not a configuration that will allow the
VDE to function. Reparent it to pll_c3 instead to make sure the hardware
can actually decode video content.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
0 files changed, 0 insertions, 0 deletions