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| author | Xingyu Wu <[email protected]> | 2023-07-17 02:30:37 +0000 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2023-07-19 17:08:00 +0000 |
| commit | 616bc1dea1ac8909dfcd6d32802df6fe50eddde8 (patch) | |
| tree | d39b3b35a2179eb315f5597b563f31e13d34d252 /tools/perf/scripts/python/futex-contention.py | |
| parent | dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator (diff) | |
| download | kernel-616bc1dea1ac8909dfcd6d32802df6fe50eddde8.tar.gz kernel-616bc1dea1ac8909dfcd6d32802df6fe50eddde8.zip | |
clk: starfive: Add StarFive JH7110 PLL clock driver
Add driver for the StarFive JH7110 PLL clock controller
and they work by reading and setting syscon registers.
Co-developed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
0 files changed, 0 insertions, 0 deletions