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| author | Paul Cercueil <[email protected]> | 2018-06-27 12:14:59 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2018-07-06 18:47:28 +0000 |
| commit | 2b555a4b9caecfcab1b2aade176df795ceceaefa (patch) | |
| tree | 669673479270703249ca63368e52ea548a6eb7f6 /tools/perf/scripts/python/futex-contention.py | |
| parent | clk: ingenic: Fix incorrect data for the i2s clock (diff) | |
| download | kernel-2b555a4b9caecfcab1b2aade176df795ceceaefa.tar.gz kernel-2b555a4b9caecfcab1b2aade176df795ceceaefa.zip | |
clk: ingenic: Add missing flag for UDC clock
The UDC clock of the JZ4740 SoC can be gated, but the data structure
representing it was missing the CGU_CLK_GATE flag to make it work.
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
0 files changed, 0 insertions, 0 deletions