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authorSam Protsenko <[email protected]>2023-02-23 04:21:32 +0000
committerKrzysztof Kozlowski <[email protected]>2023-03-06 15:57:48 +0000
commit9a8ab39f7f8d32cf36dcd80cdaaec4998e834cf5 (patch)
tree211a2d7c73d9006b7338e62ff94386f571cccb29 /tools/perf/scripts/python/flamegraph.py
parentclk: samsung: exynos850: Implement CMU_G3D domain (diff)
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clk: samsung: exynos850: Add AUD and HSI main gate clocks
Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Signed-off-by: Sam Protsenko <[email protected]> Reviewed-by: Chanho Park <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
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