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| author | Icenowy Zheng <[email protected]> | 2019-05-21 16:10:59 +0000 |
|---|---|---|
| committer | Rob Herring <[email protected]> | 2019-05-22 19:19:59 +0000 |
| commit | d4db6c089099d38166752c93d9d165fb7526f1e5 (patch) | |
| tree | fd476cfcd3634589b764a77be84767345f153252 /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | drm: remove prime sg_table caching (diff) | |
| download | kernel-d4db6c089099d38166752c93d9d165fb7526f1e5.tar.gz kernel-d4db6c089099d38166752c93d9d165fb7526f1e5.zip | |
dt-bindings: gpu: add bus clock for Mali Midgard GPUs
Some SoCs adds a bus clock gate to the Mali Midgard GPU.
Add the binding for the bus clock.
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Clément Péron <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions