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| author | Xingyu Wu <[email protected]> | 2023-07-13 11:38:56 +0000 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2023-07-19 17:08:00 +0000 |
| commit | 9b3938c0b81e79e1c0e1a3e95be3e12efd8c771b (patch) | |
| tree | be1dd5142a92968b5756b99893f4f69ea145dc0d /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset gene... (diff) | |
| download | kernel-9b3938c0b81e79e1c0e1a3e95be3e12efd8c771b.tar.gz kernel-9b3938c0b81e79e1c0e1a3e95be3e12efd8c771b.zip | |
dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.
Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions