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| author | Mika Westerberg <[email protected]> | 2018-09-18 15:36:21 +0000 |
|---|---|---|
| committer | Linus Walleij <[email protected]> | 2018-09-20 15:21:52 +0000 |
| commit | 96147db1e1dff83679e71ac92193cbcab761a14c (patch) | |
| tree | fae535aee78745d578e851c541c611389c11a5cf /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | pinctrl: cannonlake: Fix gpio base for GPP-E (diff) | |
| download | kernel-96147db1e1dff83679e71ac92193cbcab761a14c.tar.gz kernel-96147db1e1dff83679e71ac92193cbcab761a14c.zip | |
pinctrl: intel: Do pin translation in other GPIO operations as well
For some reason I thought GPIOLIB handles translation from GPIO ranges
to pinctrl pins but it turns out not to be the case. This means that
when GPIOs operations are performed for a pin controller having a custom
GPIO base such as Cannon Lake and Ice Lake incorrect pin number gets
used internally.
Fix this in the same way we did for lock/unlock IRQ operations and
translate the GPIO number to pin before using it.
Fixes: a60eac3239f0 ("pinctrl: intel: Allow custom GPIO base for pad groups")
Reported-by: Rajat Jain <[email protected]>
Signed-off-by: Mika Westerberg <[email protected]>
Tested-by: Rajat Jain <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions