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| author | Thierry Reding <[email protected]> | 2018-06-11 08:18:53 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2018-07-09 00:03:59 +0000 |
| commit | 26f8590c4a1f7bd30ef9b9d713388bd96eb43d16 (patch) | |
| tree | 4ad85c8ec1f234365eaa616101a300ef50c3a8af /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | Linux 4.18-rc1 (diff) | |
| download | kernel-26f8590c4a1f7bd30ef9b9d713388bd96eb43d16.tar.gz kernel-26f8590c4a1f7bd30ef9b9d713388bd96eb43d16.zip | |
clk: tegra: Make vic03 a child of pll_c3
By default, the vic03 clock is a child of pll_m but that runs at 924 MHz
which is too fast for VIC. Make vic03 a child of pll_c3 by default so it
will run at a supported frequency.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions