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| author | Guo Ren <[email protected]> | 2020-03-31 15:45:52 +0000 |
|---|---|---|
| committer | Guo Ren <[email protected]> | 2020-03-31 16:06:40 +0000 |
| commit | 9c0e343d7654a329d1f9b53d253cbf7fb6eff85d (patch) | |
| tree | a51bfcdbb5d8191b5a1414f9b798b4f38f0e8efa /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | csky/ftrace: Fixup ftrace_modify_code deadlock without CPU_HAS_ICACHE_INS (diff) | |
| download | kernel-9c0e343d7654a329d1f9b53d253cbf7fb6eff85d.tar.gz kernel-9c0e343d7654a329d1f9b53d253cbf7fb6eff85d.zip | |
csky: Fixup get wrong psr value from phyical reg
We should get psr value from regs->psr in stack, not directly get
it from phyiscal register then save the vector number in
tsk->trap_no.
Signed-off-by: Guo Ren <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions