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authorRob Herring <[email protected]>2020-04-29 19:19:21 +0000
committerWill Deacon <[email protected]>2020-04-29 20:33:19 +0000
commit184dbc152e398d7136dabd59ed3f5c5521935712 (patch)
tree130a1ded77827ca062bf4e271c16796eecdf124f /tools/perf/scripts/python/event_analyzing_sample.py
parentarm64: docs: Mandate that the I-cache doesn't hold stale kernel text (diff)
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arm64: silicon-errata.rst: Sort the Cortex-A55 entries
The Arm silicon errata list is mostly sorted by CPU name with the exception of Cortex-A55, so let's sort it before adding more entries. Signed-off-by: Rob Herring <[email protected]> Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
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