diff options
| author | Tony W Wang-oc <[email protected]> | 2019-06-18 08:37:29 +0000 |
|---|---|---|
| committer | Thomas Gleixner <[email protected]> | 2019-06-22 09:45:58 +0000 |
| commit | f8c0e061cb83bd528ff0843e717bcebc846d4838 (patch) | |
| tree | a394087b89b21832b92d37728faf51659cfee2ae /tools/perf/scripts/python/compaction-times.py | |
| parent | ACPI, x86: Add Zhaoxin processors support for NONSTOP TSC (diff) | |
| download | kernel-f8c0e061cb83bd528ff0843e717bcebc846d4838.tar.gz kernel-f8c0e061cb83bd528ff0843e717bcebc846d4838.zip | |
x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3
Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.
Signed-off-by: Tony W Wang-oc <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Cc: "[email protected]" <[email protected]>
Cc: "[email protected]" <[email protected]>
Cc: "[email protected]" <[email protected]>
Cc: "[email protected]" <[email protected]>
Cc: David Wang <[email protected]>
Cc: "Cooper Yan(BJ-RD)" <[email protected]>
Cc: "Qiyuan Wang(BJ-RD)" <[email protected]>
Cc: "Herry Yang(BJ-RD)" <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/compaction-times.py')
0 files changed, 0 insertions, 0 deletions