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| author | Arınç ÜNAL <[email protected]> | 2023-02-11 10:49:15 +0000 |
|---|---|---|
| committer | Thomas Bogendoerfer <[email protected]> | 2023-02-17 10:58:37 +0000 |
| commit | bae833414bfe6a33f6d55d5e0eb38e5989c6fe7b (patch) | |
| tree | ecea91381b3dc8241ea9007d3064ca632097c384 /tools/perf/scripts/python/compaction-times.py | |
| parent | mips: dts: align LED node names with dtschema (diff) | |
| download | kernel-bae833414bfe6a33f6d55d5e0eb38e5989c6fe7b.tar.gz kernel-bae833414bfe6a33f6d55d5e0eb38e5989c6fe7b.zip | |
mips: dts: ralink: mt7621: add port@5 as CPU port
On MT7621AT, MT7621DAT, and MT7621ST SoCs, port 5 of the MT7530 switch is
connected to the second MAC of the SoC as a CPU port. Add the port and set
up the second MAC on the bindings. Revert PHY muxing on GB-PC1.
There's an external PHY connected to the second MAC of the SoC on GB-PC2,
therefore, disable port@5 for this device.
Signed-off-by: Arınç ÜNAL <[email protected]>
Acked-by: Sergio Paracuellos <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/compaction-times.py')
0 files changed, 0 insertions, 0 deletions