diff options
| author | Li Ming <[email protected]> | 2025-07-11 03:23:56 +0000 |
|---|---|---|
| committer | Dave Jiang <[email protected]> | 2025-07-11 16:46:53 +0000 |
| commit | 03ff65c02559e8da32be231d7f10fe899233ceae (patch) | |
| tree | a46c0f2e44919cdea6be53befba36c9751aeb0ae /tools/perf/scripts/python/compaction-times.py | |
| parent | cxl/core: Introduce a new helper cxl_resource_contains_addr() (diff) | |
| download | kernel-03ff65c02559e8da32be231d7f10fe899233ceae.tar.gz kernel-03ff65c02559e8da32be231d7f10fe899233ceae.zip | |
cxl/edac: Fix wrong dpa checking for PPR operation
Per Table 8-143. "Get Partition Info Output Payload" in CXL r3.2 section
8.2.10.9.2.1 "Get Partition Info(Opcode 4100h)", DPA 0 is a valid
address of a CXL device. However, cxl_do_ppr() considers it as an
invalid address, so that user will get an -EINVAL when user calls the
sysfs interface of the edac driver to trigger a Post Package Repair(PPR)
operation for DPA 0 on a CXL device. The correct implementation should
be checking if the input DPA is in the DPA range of the CXL device.
Fixes: be9b359e056a ("cxl/edac: Add CXL memory device soft PPR control feature")
Signed-off-by: Li Ming <[email protected]>
Tested-by: Shiju Jose <[email protected]>
Reviewed-by: Shiju Jose <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
Reviewed-by: Alison Schofield <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Dave Jiang <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/compaction-times.py')
0 files changed, 0 insertions, 0 deletions