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| author | Mark Brown <[email protected]> | 2023-08-23 18:54:43 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2023-08-23 18:54:43 +0000 |
| commit | fd53c16b392dd4e1d6997a0e2425895d4cb29ff8 (patch) | |
| tree | 336a0b2b20c6d59e22113140b02c9344f3cdf650 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | ASoC: audio-graph-card2: add comment for format property (diff) | |
| parent | ASoC: rsnd: setup BRGCKR/BRRA/BRRB on rsnd_adg_clk_control() (diff) | |
| download | kernel-fd53c16b392dd4e1d6997a0e2425895d4cb29ff8.tar.gz kernel-fd53c16b392dd4e1d6997a0e2425895d4cb29ff8.zip | |
ASoC: rsnd: tidyup ADG
Merge series from Kuninori Morimoto <[email protected]>:
Renesas Sound has ADG for clock control. Basically it needs
accurately divisible external input clock. But sometimes
sometimes it doesn't have to be accurate for some reason.
We can use ADG clk_i for such case. It came from CPG as
very high rate clock, but is not accurately divisible for
48kHz/44.1kHz rate, but enough for approximate rate.
This patch set support such use case.
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions