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| author | Marcin Bachry <[email protected]> | 2021-07-22 02:58:58 +0000 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2021-08-19 15:21:53 +0000 |
| commit | e0bff43220925b7e527f9d3bc9f5c624177c959e (patch) | |
| tree | 49d1bbb8d2ca55d2e5cd3e3900b7aa223f11db43 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | MAINTAINERS: Add Jim Quinlan et al as Broadcom STB PCIe maintainers (diff) | |
| download | kernel-e0bff43220925b7e527f9d3bc9f5c624177c959e.tar.gz kernel-e0bff43220925b7e527f9d3bc9f5c624177c959e.zip | |
PCI: Increase D3 delay for AMD Renoir/Cezanne XHCI
The Renoir XHCI controller apparently doesn't resume reliably with the
standard D3hot-to-D0 delay. Increase it to 20ms.
[Alex: I talked to the AMD USB hardware team and the AMD Windows team and
they are not aware of any HW errata or specific issues. The HW works fine
in Windows. I was told Windows uses a rather generous default delay of
100ms for PCI state transitions.]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Marcin Bachry <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: [email protected]
Cc: Mario Limonciello <[email protected]>
Cc: Prike Liang <[email protected]>
Cc: Shyam Sundar S K <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions