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| author | Xingyu Wu <[email protected]> | 2023-07-13 11:38:58 +0000 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2023-07-19 17:08:00 +0000 |
| commit | a097a5ec14dff59568b1e6c8bd8cc37a21d8811f (patch) | |
| tree | efb36e0ae95e319985148b93dac7c3d888e8c30a /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
| parent | dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset ... (diff) | |
| download | kernel-a097a5ec14dff59568b1e6c8bd8cc37a21d8811f.tar.gz kernel-a097a5ec14dff59568b1e6c8bd8cc37a21d8811f.zip | |
dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.
Acked-by: Palmer Dabbelt <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions