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| author | Kim Phillips <[email protected]> | 2023-07-20 19:47:27 +0000 |
|---|---|---|
| committer | Borislav Petkov (AMD) <[email protected]> | 2023-07-22 16:04:22 +0000 |
| commit | fd470a8beed88440b160d690344fbae05a0b9b1b (patch) | |
| tree | 2355c8b0ee8742bf5c8c5f121450734bb3bf97e0 /tools/perf/builtin-script.c | |
| parent | x86/MCE/AMD: Decrement threshold_bank refcount when removing threshold blocks (diff) | |
| download | kernel-fd470a8beed88440b160d690344fbae05a0b9b1b.tar.gz kernel-fd470a8beed88440b160d690344fbae05a0b9b1b.zip | |
x86/cpu: Enable STIBP on AMD if Automatic IBRS is enabled
Unlike Intel's Enhanced IBRS feature, AMD's Automatic IBRS does not
provide protection to processes running at CPL3/user mode, see section
"Extended Feature Enable Register (EFER)" in the APM v2 at
https://bugzilla.kernel.org/attachment.cgi?id=304652
Explicitly enable STIBP to protect against cross-thread CPL3
branch target injections on systems with Automatic IBRS enabled.
Also update the relevant documentation.
Fixes: e7862eda309e ("x86/cpu: Support AMD Automatic IBRS")
Reported-by: Tom Lendacky <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/builtin-script.c')
0 files changed, 0 insertions, 0 deletions