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| author | Furong Xu <[email protected]> | 2025-01-15 03:27:04 +0000 |
|---|---|---|
| committer | Paolo Abeni <[email protected]> | 2025-01-16 11:14:23 +0000 |
| commit | 2a2931517c9ac482b617d56ca0b961d2f2776366 (patch) | |
| tree | c5449dabeb9aba7a91fe0a636fbe5a60426e1979 /tools/net/ynl/pyynl/cli.py | |
| parent | net: stmmac: Set page_pool_params.max_len to a precise size (diff) | |
| download | kernel-2a2931517c9ac482b617d56ca0b961d2f2776366.tar.gz kernel-2a2931517c9ac482b617d56ca0b961d2f2776366.zip | |
net: stmmac: Optimize cache prefetch in RX path
Current code prefetches cache lines for the received frame first, and
then dma_sync_single_for_cpu() against this frame, this is wrong.
Cache prefetch should be triggered after dma_sync_single_for_cpu().
This patch brings ~2.8% driver performance improvement in a TCP RX
throughput test with iPerf tool on a single isolated Cortex-A65 CPU
core, 2.84 Gbits/sec increased to 2.92 Gbits/sec.
Signed-off-by: Furong Xu <[email protected]>
Reviewed-by: Alexander Lobakin <[email protected]>
Reviewed-by: Yanteng Si <[email protected]>
Signed-off-by: Paolo Abeni <[email protected]>
Diffstat (limited to 'tools/net/ynl/pyynl/cli.py')
0 files changed, 0 insertions, 0 deletions