diff options
| author | Maxime Chevallier <[email protected]> | 2023-06-01 14:14:51 +0000 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2023-06-05 08:56:36 +0000 |
| commit | 642af0f92cbe01c4b05eb38a0fe94867a3798b34 (patch) | |
| tree | 02476954314f58e1eb89f23151df3876d6fb4cd2 /tools/net/ynl/generated/netdev-user.c | |
| parent | ipv6: lower "link become ready"'s level message (diff) | |
| download | kernel-642af0f92cbe01c4b05eb38a0fe94867a3798b34.tar.gz kernel-642af0f92cbe01c4b05eb38a0fe94867a3798b34.zip | |
net: mdio: Introduce a regmap-based mdio driver
There exists several examples today of devices that embed an ethernet
PHY or PCS directly inside an SoC. In this situation, either the device
is controlled through a vendor-specific register set, or sometimes
exposes the standard 802.3 registers that are typically accessed over
MDIO.
As phylib and phylink are designed to use mdiodevices, this driver
allows creating a virtual MDIO bus, that translates mdiodev register
accesses to regmap accesses.
The reason we use regmap is because there are at least 3 such devices
known today, 2 of them are Altera TSE PCS's, memory-mapped, exposed
with a 4-byte stride in stmmac's dwmac-socfpga variant, and a 2-byte
stride in altera-tse. The other one (nxp,sja1110-base-tx-mdio) is
exposed over SPI.
Signed-off-by: Maxime Chevallier <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/net/ynl/generated/netdev-user.c')
0 files changed, 0 insertions, 0 deletions