diff options
| author | Srinivas Kandagatla <[email protected]> | 2022-02-24 11:17:10 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2022-02-25 13:51:06 +0000 |
| commit | 31bd0db84c6010cd6cf38048570b51aaae26d91d (patch) | |
| tree | 7840c5e7133b35cc0920aadd58b6e47adb5d8e72 /sound | |
| parent | ASoC: codecs: wsa-macro: setup soundwire clks correctly (diff) | |
| download | kernel-31bd0db84c6010cd6cf38048570b51aaae26d91d.tar.gz kernel-31bd0db84c6010cd6cf38048570b51aaae26d91d.zip | |
ASoC: codecs: tx-macro: setup soundwire clks correctly
For SoundWire Frame sync to be generated correctly we need both MCLK
and MCLKx2 (npl). Without pm runtime enabled these two clocks will remain on,
however after adding pm runtime support its possible that NPl clock could be
turned off even when SoundWire controller is active.
Fix this by enabling mclk and npl clk when SoundWire clks are enabled.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/codecs/lpass-tx-macro.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c index cd2a8c300197..27a8774e6360 100644 --- a/sound/soc/codecs/lpass-tx-macro.c +++ b/sound/soc/codecs/lpass-tx-macro.c @@ -1690,6 +1690,13 @@ static int swclk_gate_enable(struct clk_hw *hw) { struct tx_macro *tx = to_tx_macro(hw); struct regmap *regmap = tx->regmap; + int ret; + + ret = clk_prepare_enable(tx->mclk); + if (ret) { + dev_err(tx->dev, "failed to enable mclk\n"); + return ret; + } tx_macro_mclk_enable(tx, true); if (tx->reset_swr) @@ -1717,6 +1724,7 @@ static void swclk_gate_disable(struct clk_hw *hw) CDC_TX_SWR_CLK_EN_MASK, 0x0); tx_macro_mclk_enable(tx, false); + clk_disable_unprepare(tx->mclk); } static int swclk_gate_is_enabled(struct clk_hw *hw) @@ -1753,7 +1761,7 @@ static int tx_macro_register_mclk_output(struct tx_macro *tx) struct clk_init_data init; int ret; - parent_clk_name = __clk_get_name(tx->mclk); + parent_clk_name = __clk_get_name(tx->npl); init.name = clk_name; init.ops = &swclk_gate_ops; |