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| author | Russell King <[email protected]> | 2010-04-09 14:00:11 +0000 |
|---|---|---|
| committer | Russell King <[email protected]> | 2010-04-09 14:00:11 +0000 |
| commit | 85b3cce880a19e78286570d5fd004cc3cac06f57 (patch) | |
| tree | bf251707e89682972089dfec185ca5625db88e34 /scripts/mod/file2alias.c | |
| parent | ARM: 6043/1: AT91 slow-clock resume: Don't wait for a disabled PLL to lock (diff) | |
| download | kernel-85b3cce880a19e78286570d5fd004cc3cac06f57.tar.gz kernel-85b3cce880a19e78286570d5fd004cc3cac06f57.zip | |
ARM: Fix ioremap_cached()/ioremap_wc() for SMP platforms
Write combining/cached device mappings are not setting the shared bit,
which could potentially cause problems on SMP systems since the cache
lines won't participate in the cache coherency protocol.
Signed-off-by: Russell King <[email protected]>
Tested-by: Santosh Shilimkar <[email protected]>
Diffstat (limited to 'scripts/mod/file2alias.c')
0 files changed, 0 insertions, 0 deletions