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authorFabrizio Castro <[email protected]>2025-04-23 14:34:21 +0000
committerVinod Koul <[email protected]>2025-05-14 14:30:40 +0000
commit7de873201c44bff5b42f2e560098d463843b8a4c (patch)
tree2f756768a7f19361419eb0668e74ba577c5832b9 /scripts/git-resolve.sh
parentdmaengine: sh: rz-dmac: Allow for multiple DMACs (diff)
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dmaengine: sh: rz-dmac: Add RZ/V2H(P) support
The DMAC IP found on the Renesas RZ/V2H(P) family of SoCs is similar to the version found on the Renesas RZ/G2L family of SoCs, but there are some differences: * It only uses one register area * It only uses one clock * It only uses one reset * Instead of using MID/IRD it uses REQ No * It is connected to the Interrupt Control Unit (ICU) * On the RZ/G2L there is only 1 DMAC, on the RZ/V2H(P) there are 5 Add specific support for the Renesas RZ/V2H(P) family of SoC by tackling the aforementioned differences. Signed-off-by: Fabrizio Castro <[email protected]> Reviewed-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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