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authorSteffen Bätz <[email protected]>2024-05-08 07:29:44 +0000
committerPaolo Abeni <[email protected]>2024-05-09 09:48:20 +0000
commit6e7ffa180a532b6fe2e22aa6182e02ce988a43aa (patch)
tree31a9b432b44f53aee4291bb69199e3dfae6baaf9 /scripts/generate_rust_target.rs
parentnet: dsa: mv88e6xxx: add phylink_get_caps for the mv88e6320/21 family (diff)
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net: dsa: mv88e6xxx: read cmode on mv88e6320/21 serdes only ports
On the mv88e6320 and 6321 switch family, port 0/1 are serdes only ports. Modified the mv88e6352_get_port4_serdes_cmode function to pass a port number since the register set of the 6352 is equal on the 6320/21. Signed-off-by: Steffen Bätz <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
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