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| author | Conor Dooley <[email protected]> | 2025-05-12 13:48:14 +0000 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2025-05-12 15:53:29 +0000 |
| commit | d58a73c96d8ae87936579689af1dd60a09bda432 (patch) | |
| tree | 1f847191c7edb43dae93baa5f72df246a365563f /scripts/gcc-plugins/randomize_layout_plugin.c | |
| parent | cache: sifive_ccache: Add ESWIN EIC7700 support (diff) | |
| download | kernel-d58a73c96d8ae87936579689af1dd60a09bda432.tar.gz kernel-d58a73c96d8ae87936579689af1dd60a09bda432.zip | |
dt-bindings: cache: add specific RZ/Five compatible to ax45mp
When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.
Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.
Acked-by: Ben Zong-You Xie <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Diffstat (limited to 'scripts/gcc-plugins/randomize_layout_plugin.c')
0 files changed, 0 insertions, 0 deletions