diff options
| author | Shanker Donthineni <[email protected]> | 2017-10-09 16:46:55 +0000 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2017-10-13 15:30:58 +0000 |
| commit | 30ae9610d275f8f03f5bf7612ce71d8af6fc400b (patch) | |
| tree | a297a65bef8c77e07e010f02bf2e855fccc2b020 /scripts/gcc-plugins/gcc-generate-rtl-pass.h | |
| parent | irqchip/gic-v3-its: Fix the incorrect parsing of VCPU table size (diff) | |
| download | kernel-30ae9610d275f8f03f5bf7612ce71d8af6fc400b.tar.gz kernel-30ae9610d275f8f03f5bf7612ce71d8af6fc400b.zip | |
irqchip/gic-v3-its: Add missing changes to support 52bit physical address
The current ITS driver works fine as long as normal memory and GICR
regions are located within the lower 48bit (>=0 && <2^48) physical
address space. Some of the registers GICR_PEND/PROP, GICR_VPEND/VPROP
and GITS_CBASER are handled properly but not all when configuring
the hardware with 52bit physical address.
This patch does the following changes to support 52bit PA.
-Handle 52bit PA in GITS_BASERn.
-Fix ITT_addr width to 52bits, bits[51:8].
-Fix RDbase width to 52bits, bits[51:16].
-Fix VPT_addr width to 52bits, bits[51:16].
Definition of the GITS_BASERn register when ITS PageSize is 64KB:
-Bits[47:16] of the register provide bits[47:16] of the table PA.
-Bits[15:12] of the register provide bits[51:48] of the table PA.
-Bits[15:00] of the base physical address are 0.
Signed-off-by: Shanker Donthineni <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Diffstat (limited to 'scripts/gcc-plugins/gcc-generate-rtl-pass.h')
0 files changed, 0 insertions, 0 deletions