diff options
| author | Michal Simek <[email protected]> | 2025-07-24 10:57:57 +0000 |
|---|---|---|
| committer | Rob Herring (Arm) <[email protected]> | 2025-07-25 19:54:16 +0000 |
| commit | 7ce3c2713b45e349468fd5f9166f376ad9a361e3 (patch) | |
| tree | 173c0200444717f6b008c77a9c74e73bcbb03e4f /rust/helpers/xarray.c | |
| parent | dt-bindings: display: sprd,sharkl3-dsi-host: Fix missing clocks constraints (diff) | |
| download | kernel-7ce3c2713b45e349468fd5f9166f376ad9a361e3.tar.gz kernel-7ce3c2713b45e349468fd5f9166f376ad9a361e3.zip | |
dt-bindings: interrupt-controller: Add missing Xilinx INTC binding
Add missing description for AMD/Xilinx interrupt controller. The binding is
used by Microblaze before dt-binding even existed but never been
documented properly.
IP acts as primary interrupt controller on Microblaze systems or can be
used as secondary interrupt controller on ARM based systems like Zynq,
ZynqMP, Versal or Versal Gen 2. Also as secondary interrupt controller on
Microblaze-V (Risc-V) systems.
Over the years IP exists in multiple variants based on attached bus as OPB,
PLB or AXI that's why generic filename is used.
Property xlnx,kind-of-intr is in hex because every bit position corresponds
to interrupt line. Controller support mixing edge or level interrupts
together and this is the property which distinguish them.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/2b9d4a3a693f501d420da88b8418732ba9def877.1753354675.git.michal.simek@amd.com
Signed-off-by: Rob Herring (Arm) <[email protected]>
Diffstat (limited to 'rust/helpers/xarray.c')
0 files changed, 0 insertions, 0 deletions