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| author | Mihai Sain <[email protected]> | 2025-06-19 07:06:35 +0000 |
|---|---|---|
| committer | Claudiu Beznea <[email protected]> | 2025-07-05 07:43:30 +0000 |
| commit | 4101c8274b093519019761e174c81980f7b30f56 (patch) | |
| tree | b096c39c1b52dd315ff6f5c8aca1bc9d697ce0d2 /rust/helpers/vmalloc.c | |
| parent | ARM: dts: microchip: sama5d4: Update the cache configuration for CPU (diff) | |
| download | kernel-4101c8274b093519019761e174c81980f7b30f56.tar.gz kernel-4101c8274b093519019761e174c81980f7b30f56.zip | |
ARM: dts: microchip: sama7d65: Add cache configuration for cpu node
Describe the cache memories according with datasheet chapter 15.2:
- L1 cache configuration with 32KB for both data and instruction cache.
- L2 cache configuration with 256KB unified cache.
Before this patch the kernel reported the warning:
[ 0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0
Signed-off-by: Mihai Sain <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Claudiu Beznea <[email protected]>
Diffstat (limited to 'rust/helpers/vmalloc.c')
0 files changed, 0 insertions, 0 deletions