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| author | Jijie Shao <[email protected]> | 2025-07-22 12:54:23 +0000 |
|---|---|---|
| committer | Paolo Abeni <[email protected]> | 2025-07-24 09:27:22 +0000 |
| commit | 49ade8630f36e9dca2395592cfb0b7deeb07e746 (patch) | |
| tree | 7becd17f22064fabe91cb458bf91d54fd0873855 /rust/helpers/task.c | |
| parent | net: hns3: fixed vf get max channels bug (diff) | |
| download | kernel-49ade8630f36e9dca2395592cfb0b7deeb07e746.tar.gz kernel-49ade8630f36e9dca2395592cfb0b7deeb07e746.zip | |
net: hns3: default enable tx bounce buffer when smmu enabled
The SMMU engine on HIP09 chip has a hardware issue.
SMMU pagetable prefetch features may prefetch and use a invalid PTE
even the PTE is valid at that time. This will cause the device trigger
fake pagefaults. The solution is to avoid prefetching by adding a
SYNC command when smmu mapping a iova. But the performance of nic has a
sharp drop. Then we do this workaround, always enable tx bounce buffer,
avoid mapping/unmapping on TX path.
This issue only affects HNS3, so we always enable
tx bounce buffer when smmu enabled to improve performance.
Fixes: 295ba232a8c3 ("net: hns3: add device version to replace pci revision")
Signed-off-by: Jian Shen <[email protected]>
Signed-off-by: Jijie Shao <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Paolo Abeni <[email protected]>
Diffstat (limited to 'rust/helpers/task.c')
0 files changed, 0 insertions, 0 deletions
