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authorJann Horn <[email protected]>2025-07-02 08:32:04 +0000
committerDave Hansen <[email protected]>2025-07-09 14:46:36 +0000
commit76303ee8d54bff6d9a6d55997acd88a6c2ba63cf (patch)
tree801d76b2b86b81218b208e309be8daadde05b99c /rust/helpers/regulator.c
parentx86/CPU/AMD: Disable INVLPGB on Zen2 (diff)
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x86/mm: Disable hugetlb page table sharing on 32-bit
Only select ARCH_WANT_HUGE_PMD_SHARE on 64-bit x86. Page table sharing requires at least three levels because it involves shared references to PMD tables; 32-bit x86 has either two-level paging (without PAE) or three-level paging (with PAE), but even with three-level paging, having a dedicated PGD entry for hugetlb is only barely possible (because the PGD only has four entries), and it seems unlikely anyone's actually using PMD sharing on 32-bit. Having ARCH_WANT_HUGE_PMD_SHARE enabled on non-PAE 32-bit X86 (which has 2-level paging) became particularly problematic after commit 59d9094df3d7 ("mm: hugetlb: independent PMD page table shared count"), since that changes `struct ptdesc` such that the `pt_mm` (for PGDs) and the `pt_share_count` (for PMDs) share the same union storage - and with 2-level paging, PMDs are PGDs. (For comparison, arm64 also gates ARCH_WANT_HUGE_PMD_SHARE on the configuration of page tables such that it is never enabled with 2-level paging.) Closes: https://lore.kernel.org/r/[email protected] Fixes: cfe28c5d63d8 ("x86: mm: Remove x86 version of huge_pmd_share.") Reported-by: Vitaly Chikunov <[email protected]> Suggested-by: Dave Hansen <[email protected]> Signed-off-by: Jann Horn <[email protected]> Signed-off-by: Dave Hansen <[email protected]> Acked-by: Oscar Salvador <[email protected]> Acked-by: David Hildenbrand <[email protected]> Tested-by: Vitaly Chikunov <[email protected]> Cc:[email protected] Link: https://lore.kernel.org/all/20250702-x86-2level-hugetlb-v2-1-1a98096edf92%40google.com
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